The present invention relates to a method of manufacturing a photomask and a technique for manufacturing a semiconductor integrated circuit device. Particularly, the present invention relates to a technique effectively applicable to a photolithography (hereinafter, referred to as lithography) technique, in which a predetermined pattern is transferred onto a semiconductor wafer (hereinafter, referred to as a wafer) by the exposure using a photomask (hereinafter, referred to as a mask) in the manufacturing process of a semiconductor integrated circuit device.
With the increasing demand for further scaling down of dimensions and the integration of patterns such as an element and circuit wiring, the increase in the mask cost has become a problem. This is caused by the various factors as follows: since the scaling down of dimensions and the high accuracy are required also in mask patterns even under the circumstance where the market size of the mask manufacturing field is small and the mask manufacturing is not commercially viable, a costly pattern writing apparatus and an inspection apparatus are required and the equipment cost and the running cost thereof become enormous; it becomes necessary to introduce novel technologies such as a phase shift technology and an optical proximity correction technology; and the defect rate of the mask is increased due to the scaling down of the pattern. With the improvement in the performance of the semiconductor integrated circuit device, the total number of masks required to manufacture one semiconductor integrated circuit device tends to increase. This tendency also causes an important problem to be solved, that is, how to reduce the mask cost.
Techniques for solving such problems are disclosed in, for example, pp. 145 and 146 of xe2x80x9cNikkei Micro Device, April-2000 issuexe2x80x9d issued on Apr. 1, 2000, by the Nikkei Business Publications, Inc., pp. 142 to 152 of xe2x80x9cNikkei Micro Device, May-2000 issuexe2x80x9d issued on May 1, 2000, by the Nikkei Business Publications, Inc., Japanese Patent Application Laid-Open No. 2000-17196, and pp. 647 to 657 of xe2x80x9cOptical Microlithography XIII Mar. 1-3, 2000 Santa Clara, USAxe2x80x9d issued by PROCEEDINGS OF SPIE SPIExe2x80x94The International Society for Optical Engineering. In these descriptions, disclosed are techniques in which a mask serving as a master (master mask) having high writing accuracy in dimensions is manufactured, patterns of the master mask are transferred onto a daughter mask using a reduced projection exposure apparatus, and the pattern is transferred onto a wafer using the daughter mask. Specifically, masks (master mask and daughter mask) are manufactured according to the process as follows.
Firstly, a mask substrate for a master mask is prepared. On this mask substrate, for example, a metal film such as chromium and a resist film are deposited in this order from below. Subsequently, after a pattern twenty times as large as the design rule is written on the resist film on the master mask, the lower metal film is patterned by the etching method using a resist pattern formed by the development as an etching mask, and thus the master mask is manufactured. Thereafter, a mask substrate for the daughter mask, which is identical to that for the master mask, is prepared. Subsequently, after the mask pattern of the master mask is written on a resist film of the mask substrate for the daughter mask using the reduced projection exposure apparatus such as an i-beam stepper, the metal film is etched similarly to the case of the master mask, and thus the daughter mask is manufactured. In this technique, the costly electron beam writing system is not required. Therefore, the reduction of the mask cost can be promoted.
However, the inventors of the present invention found out that the manufacturing technique of the mask (master mask and daughter mask) described above had problems as follows.
First, an adequate consideration is not given to manufacture a mask efficiently and in a short time. Specifically, in the techniques described above, though the master mask is used only once or not more than a few times, the pattern of the master mask is formed by etching the metal film thereof similarly to the normal mask having fine patterns. Therefore, it takes much time to manufacture the master mask, resulting in the occurrence of the problem that the reduction of the manufacturing time of a semiconductor integrated circuit device is hindered. Such a problem becomes severe particularly in the manufacturing of a customized product such as an LSI. The higher the performance required to the customized product becomes, the more the number of process steps and the amount of time for its development are needed. On the other hand, existing products become outdated rapidly and a lifetime of such products is short. Therefore, demands for reducing the amount of time spent on the development and manufacturing of the product have been more and more increased. Accordingly, an important problem to be solved has caused, that is, how to manufacture a mask, which is used in the manufacturing of the customized product, efficiently and in a short time.
Second, appropriate measures are not taken to further reduce the mask cost. Specifically, in the techniques described above, since the master mask is used for the exposure only once or not more than a few times, the manufacturing cost of the master mask is increased, resulting in the occurrence of the problem that the cost reduction of a semiconductor integrated circuit device is hindered. Such a problem also becomes severe particularly in the manufacturing of a customized product. This is because the amount of production of such customized products per one kind is smaller in comparison to general-purpose products such as DRAM.
An object of the present invention is to provide a technique capable of reducing the manufacturing time of a mask.
Also, another object of the present invention is to provide a technique capable of reducing the manufacturing time of a semiconductor integrated circuit device.
Also, another object of the present invention is to provide a technique capable of reducing the mask cost.
Further, another object of the present invention is to provide a technique capable of reducing the cost of a semiconductor integrated circuit device.
Other objects and novel characteristics of the present invention will be apparent according to the description and the accompanying drawings of this specification.
The outline of the typical one of the inventions disclosed in this application will be described as follows.
Specifically, the present invention includes the step of transferring each pattern of a plurality of first masks including one or more resist masks onto a second mask by the reduced projection exposure, thereafter transferring the pattern on the second mask onto a semiconductor wafer by the reduced projection exposure.
In addition, the present invention includes the step of transferring each pattern of a plurality of IP masks including one or more resist masks onto a product mask by the reduced projection exposure, thereafter transferring the pattern on the product mask onto a semiconductor wafer by the reduced projection exposure.
Also, in the present invention, the product mask has a metal pattern having a light-shielding property to exposure light.
Also, in the present invention, the product mask is a resist mask.
Also, in the present invention, the product mask has both of a metal pattern having a light-shielding property to exposure light and an organic film pattern having a light-shielding property or a light-reducing property to exposure light.
Also, in the present invention, the organic film pattern is arranged in only a part of a pattern transfer region of the product mask.
Also, in the present invention, the pattern transfer region is a user logic circuit section.
Also, the present invention includes the step of: forming an organic film pattern again after removing the organic film pattern of the product mask.
Also, the present invention includes the steps of: preparing a first IP mask made of a resist film, which is a photomask used in the transfer of a memory mat or an aggregate of the memory mats; preparing a second IP mask made of a resist mask, which is a photomask used in the transfer of a peripheral circuit region of the memory mat; transferring the patterns of the first and second IP masks onto a product mask by the reduced projection exposure; and transferring the pattern on the product mask onto a semiconductor wafer by the reduced projection exposure.